1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof in which, for example, a multilayered structure inclusive of Cu wirings is applied to an MIM capacitor and, more particularly, to those in which it is taken into consideration to improve a Q value in a high-frequency circuit by lowering a resistance and prevent Cu diffusion from the multilayered structure inclusive of the Cu wirings.
2. Description of the Related Art
Generally, in a high-frequency analog integrated circuit used in a mobile communication field and so on, not only an active element but also a passive element such as a resistance and a capacitor which operate at a high speed are required since it deals with high-frequency signals. In such an integrated circuit, reduction in parasite resistance and parasite capacity is indispensable in order to achieve improvement in operation speed and reduction in power consumption. Especially in a capacitor element, an MIM (Metal-Insulator-Metal) capacitor whose parasite resistance and parasite capacity are remarkably small compared with a conventional MOS-type capacitor has come into general use.
Similarly, the application of a Cu wiring to the integrated circuit has been considered from the viewpoint of the reduction in the parasite resistance and the parasite capacity. It is the most appropriate to use a part of this Cu wiring as an electrode of the aforesaid MIM capacitor, but in ordinary manufacturing processes of the structure inclusive of the Cu wiring, an excessive film is removed by flattening a surface using a CMP method after Cu is embedded in wiring trenches. In order to obtain optimum device performance, it is necessary to minimize polishing of Cu in the wiring trenches and uniformly flatten the surface.
However, barrier metals to prevent Cu diffusion to an oxide film are formed in the wiring trenches, and polishing ratios of a barrier metal layer comprised of a hard material such as TaN and a Cu layer comprised of a soft material greatly differ from each other. Consequently, there is a concern about a problem of so-called dishing that a recessed portion is made on the surface of the Cu layer by a CPM process.
This dishing problem is especially distinguished when the Cu layer with a large surface area such as an electrode section of a capacitor is to be formed. Therefore, it is very difficult to form the electrode section of the MIM capacitor by a Cu film.